DocumentCode
1423221
Title
A new approach to built-in self-testable datapath synthesis based on integer linear programming
Author
Kim, Han Bin ; Ha, Dong Sam ; Takahashi, Takeshi ; Yamaguchi, Takahiro J.
Author_Institution
Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Volume
8
Issue
5
fYear
2000
Firstpage
594
Lastpage
605
Abstract
The focus of high-level built-in self-test (BIST) synthesis is register assignment, which involves system register assignment, BIST register assignment, and interconnection assignment. To reduce the complexity involved in the assignment process, existing high-level BIST synthesis methods decouple the three tasks and perform the tasks sequentially at the cost of global optimality. They also try to achieve only one objective: minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we propose a new approach to the BIST data path synthesis based on integer linear programming that performs the three register assignment tasks concurrently to yield optimal designs. In addition, our approach finds an optimal register assignment for each k-test session. Therefore, it offers a range of designs with different figures of merit in area and test time. Our experimental results show that our method successfully synthesizes a BIST circuit for every k-test session for all six circuits experimented. All the BIST circuits are better in area overhead than those generated by existing high-level BIST synthesis methods.
Keywords
VLSI; built-in self test; circuit CAD; design for testability; high level synthesis; integer programming; integrated circuit design; integrated circuit testing; linear programming; BIST data path synthesis; BIST register assignment; DFT; area overhead; built-in self-testable datapath synthesis; high-level BIST synthesis; integer linear programming; interconnection assignment; k-test session; optimal designs; system register assignment; Built-in self-test; Circuit synthesis; Circuit testing; Flow graphs; High level synthesis; Integer linear programming; Integrated circuit interconnections; Logic design; Logic programming; Registers;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.894164
Filename
894164
Link To Document