DocumentCode
1423246
Title
Analysis of power dissipation in double edge-triggered flip-flops
Author
Strollo, Antonio G M ; Napoli, Ettore ; Cimino, Carlo
Author_Institution
Dept. of Electron. & Telecommun., Naples Univ., Italy
Volume
8
Issue
5
fYear
2000
Firstpage
624
Lastpage
629
Abstract
A comprehensive analysis of double edge triggered (DET) flip-flops´ power dissipation, taking into account input signal statistics, is presented in this paper. It is shown that using DET instead of a single edge-triggered flip-flop may result in significant energy savings if the input signal has reduced activity. On the other hand, the high switching rate of DET internal nodes may result in larger power dissipation if the input signal has a high transition probability or significant glitching.
Keywords
CMOS digital integrated circuits; VLSI; flip-flops; integrated circuit modelling; low-power electronics; double edge-triggered flip-flops; energy savings; glitching; high switching rate; high transition probability; input glitch analysis; input signal statistics; internal nodes; power consumption model; power dissipation analysis; switching activity; Circuits; Clocks; Energy consumption; Flip-flops; Frequency; Latches; Power dissipation; Signal analysis; Statistical analysis; Very large scale integration;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.894168
Filename
894168
Link To Document