Title :
Improvement of Poly-Pimple-Induced Device Mismatch on 6T-SRAM at 65-nm CMOS Technology
Author :
Hu, Chan-Yuan ; Chen, Jone F. ; Chen, Shih-Chih ; Chang, Shoou-Jinn ; Lee, Kay-Ming ; Lee, Chih-Ping
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fDate :
4/1/2010 12:00:00 AM
Abstract :
An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.
Keywords :
CMOS memory circuits; SRAM chips; built-in self test; etching; integrated circuit noise; integrated circuit testing; 6T-SRAM; CMOS technology; etching method; memory built-in self-test; poly-pimple-induced device mismatch; scan chain; size 65 nm; static noise margin; Built-in self-test; CMOS process; CMOS technology; Circuit noise; Circuits and systems; Crystal microstructure; Etching; Grain size; MOSFET circuits; Microelectronics; 6T-SRAM; Memory built-in self-test (MBIST); SCAN; static noise margin (SNM);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2010.2041285
