DocumentCode :
1423471
Title :
Fault tolerance in VLSI circuits
Author :
Koren, Israel ; Singh, Adit D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Volume :
23
Issue :
7
fYear :
1990
fDate :
7/1/1990 12:00:00 AM
Firstpage :
73
Lastpage :
83
Abstract :
The defects that can occur when manufacturing VLSI ICs and the faults that can result are described. Some commonly used restructuring techniques for avoiding defective components are discussed. Several defect-tolerant designs of memory ICs, logic ICs, and wafer-scale circuits are presented. Yield models for predicting the yield of chips with redundancy are introduced, and the optimal amount of redundancy is determined.<>
Keywords :
VLSI; electronic engineering computing; fault tolerant computing; VLSI circuits; defect-tolerant designs; defective components; wafer-scale circuits; yield models; Circuit faults; Costs; Electronic switching systems; Fabrication; Fault tolerance; Integrated circuit interconnections; Manufacturing; Redundancy; Switches; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer
Publisher :
ieee
ISSN :
0018-9162
Type :
jour
DOI :
10.1109/2.56854
Filename :
56854
Link To Document :
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