DocumentCode
1423564
Title
Multilevel circuit partitioning
Author
Alpert, Charles J. ; Huang, Jen-Hsin ; Kahng, Andrew B.
Author_Institution
IBM Austin Res. Lab., TX, USA
Volume
17
Issue
8
fYear
1998
fDate
8/1/1998 12:00:00 AM
Firstpage
655
Lastpage
667
Abstract
Many previous works in partitioning have used some underlying clustering algorithm to improve performance. As problem sizes reach new levels of complexity, a single application of a clustering algorithm is insufficient to produce excellent solutions. Recent work has illustrated the promise of multilevel approaches. A multilevel partitioning algorithm recursively clusters the instance until its size is smaller than a given threshold, then unclusters the instance, while applying a partitioning refinement algorithm. In this paper, we propose a new multilevel partitioning algorithm that exploits some of the latest innovations of classical iterative partitioning approaches. Our method also uses a new technique to control the number of levels in our matching-based clustering algorithm. Experimental results show that our heuristic outperforms numerous existing bipartitioning heuristics with improvements ranging from 6.9 to 27.9% for 100 runs and 3.0 to 20.6% for just ten runs (while also using less CPU time). Further, our algorithm generates solutions better than the best known mincut bipartitionings for seven of the ACM/SIGDA benchmark circuits, including golem3 (which has over 100000 cells). We also present quadrisection results which compare favorably to the partitionings obtained by the GORDIAN cell placement tool. Our work in multilevel quadrisection has been used as the basis for an effective cell placement package
Keywords
circuit layout CAD; integrated circuit layout; iterative methods; IC design; bipartitioning; cell placement; clustering algorithm; iterative partitioning; matching; multilevel circuit partitioning; quadrisection; Associate members; Central Processing Unit; Circuits; Clustering algorithms; Design optimization; Iterative algorithms; Iterative methods; Packaging; Partitioning algorithms; Technological innovation;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.712098
Filename
712098
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