Title :
Efficient BIST TPG design and test set compaction via input reduction
Author :
Chen, Chih-Ang ; Gupta, Sandeep K.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fDate :
8/1/1998 12:00:00 AM
Abstract :
A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (⩽230) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%
Keywords :
automatic testing; built-in self test; fault diagnosis; integrated circuit testing; logic testing; BIST TPG design; area overhead; benchmark circuits; compatible inputs; detectable stuck-at faults; deterministic test set; fault coverage; input reduction; inversely compatible inputs; test application time; test pattern generator; test set compaction; Automatic testing; Built-in self-test; Circuit analysis; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Signal generators; Test pattern generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on