DocumentCode :
1423945
Title :
Development of 3-D Silicon Module With TSV for System in Packaging
Author :
Khan, Navas ; Rao, Vempati Srinivasa ; Lim, Samuel ; We, Ho Soon ; Lee, Vincent ; Zhang, Xiaowu ; Liao, E.B. ; Nagarajan, Ranganathan ; Chai, T.C. ; Kripesh, V. ; Lau, John H.
Author_Institution :
Microsyst., Modules & Components Lab., Inst. of Microelectron., Singapore, Singapore
Volume :
33
Issue :
1
fYear :
2010
fDate :
3/1/2010 12:00:00 AM
Firstpage :
3
Lastpage :
9
Abstract :
Portable electronic products demand multifunctional module comprising of digital, radio frequency and memory functions. Through silicon via (TSV) technology provides a means of implementing complex, multifunctional integration with a higher packing density for a system in package. A 3-D silicon module with TSV has been developed in this paper. Thermo-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the barrier copper via is exposed by the backgrinding process. A two-stack silicon module is developed and module fabrication details are given in this paper. The module reliability has been evaluated under temperature cycling (-40/125??C ) and drop test.
Keywords :
chip scale packaging; elemental semiconductors; flip-chip devices; integrated circuit bonding; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; lead bonding; multichip modules; silicon; system-in-package; three-dimensional integrated circuits; 3D two-stack silicon module fabrication; Si; TSV interconnect design; backgrinding process; barrier copper via; drop test; flip chip interconnection method; functional circuits; module reliability; multifunctional integration; multifunctional modules; multiple chips; packing density; portable electronic products; silicon carrier; system in packaging; temperature cycling test; thermomechanical analysis; through-silicon via technology; via-first approach; wirebond interconnection method; 3-D packaging; system in packaging; through silicon via;
fLanguage :
English
Journal_Title :
Components and Packaging Technologies, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-3331
Type :
jour
DOI :
10.1109/TCAPT.2009.2037608
Filename :
5419075
Link To Document :
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