• DocumentCode
    1424191
  • Title

    Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism

  • Author

    Liao, Chia-Chun ; Chiang, Tsung-Yu ; Lin, Min-Chen ; Chao, Tien-Sheng

  • Author_Institution
    Dept. of Electrophys., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    31
  • Issue
    4
  • fYear
    2010
  • fDate
    4/1/2010 12:00:00 AM
  • Firstpage
    281
  • Lastpage
    283
  • Abstract
    In this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should be modulated from the point of view of stress shift rather than using the highest tensile film.
  • Keywords
    MOS integrated circuits; silicon compounds; NMOS mobility; SiN; capping layer; stress memorization technique; Contact etch-stop layer (CESL); poly amorphization implantation (PAI); strain; stress memorization technique (SMT);
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2010.2041524
  • Filename
    5419112
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1424191