DocumentCode
1424280
Title
Validating PowerPC microprocessor custom memories
Author
Krishnamurthy, Narayanan ; Martin, Andrew K. ; Abadir, Magdy S. ; Abraham, Jacob A.
Author_Institution
PowerPC Design Center, Motorola Inc., Austin, TX, USA
Volume
17
Issue
4
fYear
2000
Firstpage
61
Lastpage
76
Abstract
Due to the high cost of correcting errors in a final product, there is a growing impetus in industry towards methodologies that can yield correct designs in the first manufacturing run. Design validation methodologies that combine simulation techniques with formal reasoning can be effective in ensuring correct operation of software and hardware systems. We show why simulation is necessary to complement formal mathematical reasoning in verifying certain classes of custom designed circuits. We present a validation methodology for PowerPC custom memories based on symbolic simulation
Keywords
integrated memory circuits; logic testing; memory architecture; PowerPC; design validation; formal reasoning; microprocessor custom memories; symbolic simulation; validation methodology; Circuit simulation; Costs; Design methodology; Error correction; Hardware; Jacobian matrices; Manufacturing industries; Microprocessors; Multivalued logic; Software systems;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.895007
Filename
895007
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