DocumentCode :
1424609
Title :
A 0.02-mm 
9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology
Author :
Huang, Yen-Chuan ; Lee, Tai-Cheng
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
45
Issue :
3
fYear :
2010
fDate :
3/1/2010 12:00:00 AM
Firstpage :
610
Lastpage :
619
Abstract :
A 9-bit cyclic ADC employs a track-and-evaluation technique for enhancing the speed of residue evaluation. The proposed multiply-by-two circuit has a shorter evaluation time than the conventional design due to the application of a partial positive feedback topology. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform the 9-bit conversion. The proposed 0.02-mm2 ADC has been fabricated in 90-nm digital CMOS technology. It operates at 50 MS/s and achieves an SNDR of 50.5 dB with a power consumption of 6.9 mW from a 1.0-V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; analogue-digital conversion; complementary metal-oxide-semiconductor; conversion latency; cyclic ADC; digital CMOS technology; four clock cycles; multiply-by-two circuit; partial positive feedback topology; power 6.9 mW; residue evaluation; size 90 nm; track-and-evaluation technique; voltage 1 V; Analog-digital conversion; CMOS technology; Capacitance; Clocks; Costs; Energy consumption; Feedback circuits; Operational amplifiers; Sampling methods; Voltage; Cyclic ADC; partial positive feedback gain stage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2009.2039275
Filename :
5419180
Link To Document :
