Title :
Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory
Author :
Ikehashi, Tamio ; Imamiya, Kenichi ; Sakui, Koji
Author_Institution :
Adv. Memory Design Group, Toshiba Corp. Semicond. Co., Yokohama, Japan
fDate :
10/1/2000 12:00:00 AM
Abstract :
With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n- junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness
Keywords :
NAND circuits; circuit simulation; electrostatic discharge; flash memories; integrated circuit packaging; isolation technology; 256 Mbit; NAND flash memory; STI process; contact holes; device simulator; n- junction; robust ESD protection circuit; shallow trench isolation; CMOS process; Circuit simulation; Design methodology; Electrostatic discharge; Isolation technology; Large scale integration; MOS devices; MOSFET circuits; Protection; Robustness;
Journal_Title :
Electronics Packaging Manufacturing, IEEE Transactions on
DOI :
10.1109/6104.895068
