• DocumentCode
    1424717
  • Title

    Assembling 2-D Blocks Into 3-D Chips

  • Author

    Knechtel, Johann ; Markov, Igor L. ; Lienig, Jens

  • Author_Institution
    Inst. of Electromech. & Electron. Design, Dresden Univ. of Technol., Dresden, Germany
  • Volume
    31
  • Issue
    2
  • fYear
    2012
  • Firstpage
    228
  • Lastpage
    241
  • Abstract
    Despite numerous advantages of 3-D integrated circuits (ICs), their commercial success remains limited. In part, this is due to the wide availability of trustworthy intellectual property (IP) blocks developed for 2-D ICs and proven through repeated use. Block-based design reuse is imperative for heterogeneous 3-D ICs where memory, logic, analog, and microelectromechanical systems dies are manufactured at different technology nodes and circuit modules cannot be partitioned among several dies. In this paper, we show how to integrate 2-D IP blocks into 3-D chips without altering their layout. Experiments indicate that the overhead of proposed integration is small, which can help accelerate industry adoption of 3-D integration.
  • Keywords
    integrated circuit layout; logic circuits; microprocessor chips; three-dimensional integrated circuits; 2D IC; 2D IP blocks; 3D chips; 3D integrated circuits; analog die; block-based design reuse; circuit modules; heterogeneous 3D IC; intellectual property blocks; logic die; memory die; microelectromechanical systems die; technology nodes; IP networks; Integrated circuit interconnections; Layout; Logic gates; Pins; Through-silicon vias; 3-D IC design styles; 3-D integrated circuits (ICs); TSV islands; floorplan optimization; intellectual property (IP) blocks; through-silicon via (TSV) planning;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2011.2174640
  • Filename
    6132649