DocumentCode :
1424756
Title :
Operational analysis of synchrotron-based X-ray lithography: simulation model of wafer flows
Author :
White, K. Preston, Jr. ; Trybula, Walter J.
Author_Institution :
Dept. of Syst. Eng., Virginia Univ., Charlottesville, VA, USA
Volume :
23
Issue :
4
fYear :
2000
fDate :
10/1/2000 12:00:00 AM
Firstpage :
337
Lastpage :
344
Abstract :
A discrete-event simulation is developed that captures the processing of wafers through an advanced X-ray lithography area employing multiple synchrotrons as the source of exposure radiation. The model incorporates the best current information on unit cell design and processing. Detailed model logic implements a range of unscheduled events that represent interruption of the flow of wafer processing on the cells, as well as recovery from these downtime events. Performance measures estimated from the simulation include the weekly wafer throughput for each unit cell and the frequency of equipment states for the corresponding exposure tool. Equipment states defined in the model are based on an expansion of the SEMI E-10 guidelines to account for downtimes associated with beam charge and preventive maintenance and for uptimes associated with processing send-ahead wafers. In this paper we discuss the rationale for the simulation and consider in detail the operating assumptions embedded in the simulation model. In a companion paper we describe a simulation study in which the model is applied to compare the performance of the X-ray lithography running 200 mm and 300 mm wafers
Keywords :
X-ray lithography; discrete event simulation; semiconductor process modelling; synchrotron radiation; 200 mm; 300 mm; SEMI E-10 guidelines; beam charge; discrete-event simulation; downtime events; exposure radiation; exposure tool; multiple synchrotrons; preventive maintenance; send-ahead wafers; simulation model; synchrotron-based X-ray lithography; unit cell design; unscheduled events; wafer flows; wafer throughput; Discrete event simulation; Frequency estimation; Frequency measurement; Logic; Process design; Semiconductor device modeling; State estimation; Synchrotron radiation; Throughput; X-ray lithography;
fLanguage :
English
Journal_Title :
Electronics Packaging Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-334X
Type :
jour
DOI :
10.1109/6104.895080
Filename :
895080
Link To Document :
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