• DocumentCode
    1424811
  • Title

    VLSI implementation of visual block pattern truncation coding

  • Author

    Liu, Yuan-Chen ; Lai, Yeong-Kang ; Tsai, Tsung-Han ; Wu, Po-Cheng ; Chen, Liang-Gee

  • Author_Institution
    Dept. of Comput. & Inf. Sci., Tamsui Oxford Univ. Coll., Taipei, Taiwan
  • Volume
    44
  • Issue
    3
  • fYear
    1998
  • fDate
    8/1/1998 12:00:00 AM
  • Firstpage
    490
  • Lastpage
    499
  • Abstract
    The paper proposes a pipelined architecture of a visual block pattern truncation coding algorithm to minimize the mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for moving pictures
  • Keywords
    CMOS digital integrated circuits; VLSI; correlation methods; digital signal processing chips; image coding; pipeline processing; 0.6 micron; SPTM CMOS process; VLSI implementation; block correlated signals; image coding; mean square error; moving pictures; pipelined architecture; real-time encoding; visual block pattern truncation coding; visual block pattern truncation coding algorithm; Bit rate; Educational institutions; Geometry; Image coding; Information science; Mean square error methods; Pixel; Redundancy; Very large scale integration; Videoconference;
  • fLanguage
    English
  • Journal_Title
    Consumer Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-3063
  • Type

    jour

  • DOI
    10.1109/30.713156
  • Filename
    713156
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1424811