• DocumentCode
    1424891
  • Title

    Partitioning Interpolant-Based Verification for Effective Unbounded Model Checking

  • Author

    Cabodi, Gianpiero ; Garcia, Luz Amanda ; Murciano, Marco ; Nocco, Sergio ; Quer, Stefano

  • Author_Institution
    Dipt. di Autom. e Inf., Politec. di Torino, Turin, Italy
  • Volume
    29
  • Issue
    3
  • fYear
    2010
  • fDate
    3/1/2010 12:00:00 AM
  • Firstpage
    382
  • Lastpage
    395
  • Abstract
    Interpolant-based model checking has been shown to be effective on large verification instances, as it efficiently combines automated abstraction and reachability fixed-point checks. On the other hand, methods based on variable quantification have proved their ability to remove free inputs, thus projecting the search space over state variables. In this paper, we propose an integrated approach which combines the abstraction power of interpolation with techniques that rely on and-inverter graph (AIG) and/or binary decision diagram (BDD) representations of states, directly supporting variable quantification and fixed-point checks. The underlying idea of this combination is to adopt AIG or BDD-based quantifications to limit and restrict the search space and the complexity of the interpolant-based approach. The exploited strategies, most of which are individually well known, are integrated with a new flavor, specifically designed to improve their effectiveness on difficult verification instances. Experimental results, specifically oriented to hard-to-solve verification problems, show the robustness of our approach.
  • Keywords
    binary decision diagrams; formal verification; graph theory; interpolation; and-inverter graph; automated abstraction; binary decision diagram; interpolant-based verification; reachability fixed-point checks; unbounded model checking; variable quantification methods; Binary decision diagrams; Boolean functions; Circuits; Concrete; Data structures; Formal verification; Hardware; Interpolation; Logic; Robustness; Binary decision diagrams; formal methods; formal verification; model checking; satisfiability; symbolic techniques;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2010.2041847
  • Filename
    5419228