DocumentCode
1424896
Title
Sparc T4: A Dynamically Threaded Server-on-a-Chip
Author
Shah, Manish ; Golla, Robert ; Grohoski, Greg ; Jordan, Paul ; Barreh, Jama ; Brooks, Jeff ; Greenberg, Mark ; Levinsky, Gideon ; Luttrell, Mark ; Olson, Christopher ; Samoail, Zeid ; Smittle, Matt ; Ziaja, Tom
Volume
32
Issue
2
fYear
2012
Firstpage
8
Lastpage
19
Abstract
The Sparc T4 is the next generation of Oracle´s multicore, multithreaded 64-bit Sparc server processor. It delivers significant performance improvements over its predecessor, the Sparc T3 processor. The authors describe Sparc T4´s key features and detail the microarchitecture of the dynamically threaded S3 processor core, which is implemented on Sparc T4.
Keywords
computer architecture; microprocessor chips; multiprocessing systems; S3 processor core; Sparc T4; dynamically threaded server-on-a-chip; microarchitecture; multicore processor; multithreaded 64-bit Sparc server processor; word length 64 bit; Microprocessors; computer architecture; computer systems organization; microarchitecture implementation considerations; multicore/single-chip multiprocessors; multithreaded processors; parallel architectures; pipeline processors; processor architectures; support for multithreaded execution; support for security;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.2012.1
Filename
6133263
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