VLSI implementation of the motion estimator with two-dimensional data-reuse

Author

Lai, Yeong-Kang ; Lai, Yeong-Lin ; Liu, Yuan-Chen ; Wu, Po-Cheng ; Chen, Liang-Gee

Author_Institution

Dept. of Inf. Eng., Nat. Dong Hwa univ., Hualien, Taiwan

Volume

44

Issue

3

fYear

1998

fDate

8/1/1998 12:00:00 AM

Firstpage

623

Lastpage

629

Abstract

This paper describes the VLSI implementation with a two-dimensional (2-D) data-reuse architecture for a full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates

Keywords

CMOS digital integrated circuits; VLSI; cascade networks; digital signal processing chips; image matching; motion estimation; VLSI implementation; architecture; block sizes; cascade; data-interlacing shift-register arrays; external memory accesses; full-search block-matching algorithm; hardware utilization; motion estimator; one-dimensional processing element array; pin count; pixel rates; search ranges; throughput rate; two-dimensional data-reuse; Consumer electronics; Hardware; Motion estimation; Optimal control; Parallel processing; Registers; Systolic arrays; Throughput; Two dimensional displays; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.713173

Filename

713173