DocumentCode :
1424957
Title :
On Test Generation With Test Vector Improvement
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
29
Issue :
3
fYear :
2010
fDate :
3/1/2010 12:00:00 AM
Firstpage :
502
Lastpage :
506
Abstract :
We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cube t is generated at an arbitrary iteration of the test generation process, the test vector improvement step modifies t so as to increase the number of yet-undetected target faults that t detects. This is done in this paper using a simulation-based process. We show that even if t was generated using dynamic test compaction heuristics, it is possible to improve t further. When t is partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits of t. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults).
Keywords :
fault simulation; logic testing; vectors; dynamic test compaction heuristics; fault coverage; simulation-based process; test data compression; test generation processes; test vector improvement; yet-undetected target faults; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Energy consumption; Fault detection; Fault diagnosis; Life testing; Power generation; Test data compression; Dynamic test compaction; full-scan circuits; stuck-at faults; test cubes; test generation; transition faults;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2010.2041853
Filename :
5419239
Link To Document :
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