VLSI architecture of signal processing chip set for 42-inch DC PDP HDTV receiver

Author

Kokubun, Hideki ; Takano, Yoshimichi ; Yamamoto, Toshihiro ; Ishii, Kazuki ; Kurita, Taiichiro

Author_Institution

Japan Broadcasting Corp., Tokyo, Japan

Volume

44

Issue

3

fYear

1998

fDate

8/1/1998 12:00:00 AM

Firstpage

698

Lastpage

703

Abstract

A signal processing chip set for 42-inch DC PDP HDTV receivers has been developed. Four kinds of signal processing LSIs are fabricated with a semi-custom LSI design and 0.35 μm triple-metal CMOS technology. This paper describes the architecture of the LSI chip set and new circuit configurations to improve the picture quality. The chip set has enabled a practical PDP HDTV receiver to be fabricated

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; digital signal processing chips; flat panel displays; gas-discharge displays; high definition television; integrated circuit design; large screen displays; television receivers; video signal processing; 0.35 micron; 42 inch; 42-inch DC PDP HDTV receiver; VLSI architecture; architecture; circuit configurations; picture quality; semi-custom LSI design; signal processing LSI; signal processing chip set; triple-metal CMOS technology; CMOS technology; Circuits; Energy consumption; Gray-scale; HDTV; Large scale integration; Plasma displays; Signal processing; Signal resolution; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.713184

Filename

713184