DocumentCode :
1425113
Title :
A new PLL frequency synthesizer using multi-programmable divider
Author :
Sumi, Yasuaki ; Syoubu, Kouichi ; Obote, Shigeki ; Fukui, Yutaka ; Itoh, Yoshio
Author_Institution :
Tottori Sanyo Electr. Co. Ltd., Japan
Volume :
44
Issue :
3
fYear :
1998
fDate :
8/1/1998 12:00:00 AM
Firstpage :
827
Lastpage :
832
Abstract :
In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multiprogrammable divider are shown by theoretical considerations and experimental results
Keywords :
frequency synthesizers; phase locked loops; PLL frequency synthesizer; lock-up time; loop gain; multi-programmable divider; phase locked loop; Circuits; Delay; Detectors; Electronic mail; Frequency conversion; Frequency synthesizers; Phase detection; Phase locked loops; Transient response; Voltage-controlled oscillators;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/30.713201
Filename :
713201
Link To Document :
بازگشت