DocumentCode :
1425202
Title :
A new VLSI architecture for interleaved filtering of sampled signals
Author :
Nie, Xiaoning ; Pitscheider, Manfred ; Mehrgardt, Sonke
Author_Institution :
Semicond. Group, Siemens AG, Munich, Germany
Volume :
44
Issue :
3
fYear :
1998
fDate :
8/1/1998 12:00:00 AM
Firstpage :
926
Lastpage :
929
Abstract :
A VLSI architecture is presented for the filtering and decimation of the YUV video signals where the color difference signals U and V are sampled at the half of the sampling rate of the luminance signal Y. The poly-phase decomposition is applied to systematically derive the filter architecture. In this architecture we interleave the three signals Y, U and V with different sampling rates in such a way that the decimation filters only have to be implemented once to produce all three decimated Y, U and V signals at the output. The filter structure is canonical with respect to the number of delays. The technique has been applied to the high-speed CMOS implementation of an analog-to-digital-conversion circuit for high-quality video applications
Keywords :
CMOS digital integrated circuits; VLSI; analogue-digital conversion; digital filters; signal sampling; television receivers; video signal processing; VLSI architecture; YUV video signals; analog-to-digital-conversion circuit; color difference signals; decimation filters; filter architecture; filter structure; high-quality video applications; high-speed CMOS implementation; interleaved filtering; luminance signal; poly-phase decomposition; sampled signals; sampling rate; Circuits; Color; Filtering; Finite impulse response filter; Frequency; IIR filters; Sampling methods; Signal processing; Signal sampling; Very large scale integration;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/30.713215
Filename :
713215
Link To Document :
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