A VLSI implementation of a reconfigurable rational filter

Author

Bernacchia, G. ; Marsi, S.

Author_Institution

Dipt. di Elettrotecnica, Elettronica ed Inf., Trieste Univ., Italy

Volume

44

Issue

3

fYear

1998

fDate

8/1/1998 12:00:00 AM

Firstpage

1076

Lastpage

1085

Abstract

We propose an implementation of a reconfigurable system which exploits the features and the robustness of rational filters in order to accomplish various image processing tasks. This particular architecture is able to implement various different algorithms as noise-smoothing edge preserving filtering, interpolation, blocking artifacts removal. The architecture is structured as a bit-level pipeline and can work at frequency of 200 MHz, maintaining a quite small size of 7×5 mm²

Keywords

CMOS integrated circuits; Gaussian noise; VLSI; digital filters; image processing; interpolation; low-pass filters; pipeline arithmetic; reconfigurable architectures; smoothing methods; 200 MHz; CMOS technology; Gaussian noise; VLSI implementation; algorithms; bit-level pipeline architecture; blocking artifacts removal; frequency; image processing; interpolation; low pass filter; noise-smoothing edge preserving filtering; reconfigurable rational filter; Equations; Filtering; Image coding; Integrated circuit noise; Low pass filters; Noise figure; Noise reduction; Nonlinear filters; Polynomials; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.713237

Filename

713237