Impact of boron penetration at P/sup +/-poly/gate oxide interface on deep-submicron device reliability for dual-gate CMOS technologies

In this paper, we investigate the onset of boron penetration at the P/sup +/-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V/sub t/) and charge-to-breakdown (Q/sub BD/) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q/sub BD/ and large V/sub t/ shift have been observed due to boron penetration near the P/sup +/-poly/gate oxide interface. These results suggest that onset of boron penetration at the P/sup +/-poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF/sub 2/ implant energy and dose, and the post-implant RTA temperature.