DocumentCode :
1425755
Title :
Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers
Author :
Goh, W.L. ; Montgomery, H. ; Raza, S.H. ; Armstrong, B.M. ; Gamble, H.S.
Author_Institution :
Dept. of Electr. & Electron. Eng., Queen´s Univ., Belfast, UK
Volume :
18
Issue :
5
fYear :
1997
fDate :
5/1/1997 12:00:00 AM
Firstpage :
232
Lastpage :
234
Abstract :
Dielectrically isolated substrates containing buried highly conducting WSi2 layers are characterized for the first time using MOS capacitors. The active silicon layer is approximately 3 μm thick with a buried WSi2 layer adjacent to the isolation layer. The buried metal forms the back contact of the capacitor and excellent MOS characteristics are observed. Minority carrier lifetimes in excess of 200 μs were measured indicating the suitability of these substrates for use in device manufacture.
Keywords :
MOS capacitors; buried layers; carrier lifetime; integrated circuit measurement; integrated circuit metallisation; isolation technology; minority carriers; silicon; substrates; 200 mus; 3 micron; MOS capacitors; MOS characteristics; Si; WSi/sub 2/-SiO/sub 2/-Si; buried metallic layers; dielectrically isolated Si substrates; electrical characterization; highly conducting WSi/sub 2/ layers; isolation layer; minority carrier lifetimes; Charge carrier lifetime; Conductivity; Dielectric substrates; Integrated circuit technology; Isolation technology; MOS capacitors; Manufacturing; Silicon on insulator technology; Tungsten; Wafer bonding;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/55.568777
Filename :
568777
Link To Document :
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