DocumentCode :
1425857
Title :
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies
Author :
Alioto, Massimo ; Consoli, Elio ; Palumbo, Gaetano
Author_Institution :
Dipt. di Ing. dell´´Inf. (DII), Univ. di Siena, Siena, Italy
Volume :
19
Issue :
5
fYear :
2011
fDate :
5/1/2011 12:00:00 AM
Firstpage :
725
Lastpage :
736
Abstract :
In this paper (split into Parts I and II), an extensive comparison of existing flip-flop (FF) classes and topologies is carried out. In contrast to previous works, analysis explicitly accounts for effects that arise in nanometer technologies and affect the energy-delay-area tradeoff (e.g., leakage and the impact of layout and interconnects). Compared to previous papers on FFs comparison, the analysis involves a significantly wider range of FF classes and topologies. In particular, in this Part I, the comparison strategy, which includes the simulation setup, the energy-delay estimation methodology, and an overview of an optimum design strategy, together with the introduction of the analyzed FF classes and topologies, are reported.
Keywords :
CMOS logic circuits; delay estimation; flip-flops; integrated circuit interconnections; energy-delay estimation; energy-delay-area domain; interconnects; layout impact; nanometer CMOS flip-flops; optimum design; Analytical models; CMOS technology; Circuit topology; Clocks; Energy efficiency; Flip-flops; Integrated circuit interconnections; Integrated circuit technology; Space technology; Very large scale integration; Clocking; Logical Effort; VLSI; energy efficiency; energy-delay tradeoff; flip-flops (FFs); high speed; interconnects; leakage; low power; nanometer technologies;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2010.2041376
Filename :
5419974
Link To Document :
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