Low-voltage, high-speed circuit designs for gigabit DRAMs

Author

Lee, Kyuchan ; Kim, Changhyun ; Ryu, Dong-Ryul ; Sim, Jai-Hoon ; Lee, Sang-Bo ; Moon, Byung-Sik ; Kim, Keum-Yong ; Kim, Nam-Jong ; Yoo, Seung-Moon ; Yoon, Hongil ; Yoo, Jei-Hwan ; Cho, Soo-In

Author_Institution

Memory Div., Samsung Electron. Co. Ltd., Kyungki, South Korea

Volume

32

Issue

5

fYear

1997

fDate

5/1/1997 12:00:00 AM

Firstpage

642

Lastpage

648

Abstract

This paper describes several new circuit design techniques for low V_CC regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (ΔV_BL) as well as the V_GS margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-μm twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t_RAC) of 28 ns at V_cc=1.5 V and T=25°C has been obtained

Keywords

CMOS memory circuits; DRAM chips; ULSI; compensation; integrated circuit design; 0.18 micron; 1.5 V; 16 Mbit; 25 degC; 28 ns; access time; charge-amplifying boosted sensing scheme; cross-coupled current mirror control scheme; current sense amplifier; gigabit DRAMs; high-speed circuit designs; low-voltage circuit; row address strobe; sensing node voltage; sensing voltage difference; temperature sensitivity; temperature-compensation scheme; twin-well triple-metal CMOS process; voltage dependent boosting capacitor; Boosting; Capacitors; Circuits; Latches; Low voltage; Mirrors; Random access memory; Temperature sensors; Threshold voltage; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.568824

Filename

568824