Quantitative method for evaluating quality of analogue VLSI layout

Author

Wu, P.B. ; Mack, R.J. ; Massara, R.E.

Author_Institution

Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK

Volume

147

Issue

6

fYear

2000

fDate

12/1/2000 12:00:00 AM

Firstpage

313

Lastpage

318

Abstract

A quantitative benchmarking metric is presented for the evaluation of the quality of analogue layout. It facilitates comparisons between alternative design automation tools and, for a given tool, provides assessment of each layout instance. The quality metric reflects two principal concerns in layout design: area efficiency and net routing optimality. The algorithm has been developed to accommodate hierarchical structures, as well as flat designs. The metric allows the designer to alter the relative importance of area and routing efficiencies, although a recommendation is given on the appropriate balance. The results demonstrate the use of the metric to evaluate an automatic layout tool, and its effectiveness in providing a characterisation that corresponds to the expert designer´s judgement

Keywords

VLSI; analogue integrated circuits; circuit layout CAD; circuit optimisation; integrated circuit layout; network routing; analogue VLSI layout; area efficiency; automatic layout tool; design automation tools; flat designs; hierarchical structures; layout design; layout instance; net routing optimality; quantitative benchmarking metric; routing efficiencies;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings -

Publisher

iet

ISSN

1350-2409

Type

jour

DOI

10.1049/ip-cds:20000775

Filename

895959