Title :
A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS
Author :
Michel, Fridolin ; Steyaert, Michiel S J
Author_Institution :
Dept. of Electr. Eng., Katholieke Univ. Leuven, Heverlee, Belgium
fDate :
3/1/2012 12:00:00 AM
Abstract :
An ultra-low voltage switched-capacitor (SC) ΔΣ converter running at a record low supply voltage of only 250 mV is introduced. System level aspects are discussed and special circuit techniques described, that enable robust operation at such a low supply voltage. Using a SC biasing approach, inverter-based integrators are realized with overdrives close to the transistor threshold voltage Vth while compensating for process, voltage and temperature (PVT) variation. Biasing voltages are generated on-chip using a novel level shifting circuit, that overcomes headroom limitations due to saturation voltage Vsat. With an oversampling ratio (OSR) of 70 and a sampling frequency (fS) of 1.4 MHz at 250 mV power supply the converter achieves 61 dB SNDR in 10 kHz bandwidth while consuming a total power of 7.5 μW.
Keywords :
CMOS analogue integrated circuits; amplifiers; delta-sigma modulation; invertors; modulators; switched capacitor networks; CMOS; PVT variation; circuit techniques; inverter-based integrators; level shifting circuit; near threshold voltage-biased inverter amplifiers; oversampling ratio; power 7.5 muW; process voltage temperature variation; saturation voltage; switched-capacitor biasing approach; switched-capacitor delta-sigma modulator; transistor threshold voltage; ultra-low voltage switched-capacitor ΔΣ converter; voltage 250 mV; Gain; Inverters; Logic gates; MOS devices; Modulation; Noise; Transistors; Analog integrated circuits; analog-to-digital converter; delta-sigma; inverter-based switched capacitor circuits; low power; ultra-low voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2011.2179732
