DocumentCode
1427315
Title
Dynamic reference single-ended ECL input interface circuit for 80 Gbit/s MCMs
Author
Kawano, R. ; Yamanaka, N. ; Oki, E. ; Kawamura, T.
Author_Institution
ATM Bacbone Network Syst. Project, NTT Network Service Syst. Labs., Tokyo, Japan
Volume
34
Issue
17
fYear
1998
fDate
8/20/1998 12:00:00 AM
Firstpage
1641
Lastpage
1643
Abstract
A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To improve I/O pin number limits, the single-ended ECL circuit operates with a reference signal directly generated from the input signal itself. The reference level can change dynamically to achieve a larger noise margin for the input signal. Experimental results show that operation up to 3.4 Gbit/s with a large level margin can be attained
Keywords
asynchronous transfer mode; emitter-coupled logic; large scale integration; multichip modules; multimedia communication; reference circuits; 3.4 Gbit/s; 80 Gbit/s; I/O pin number limits; MCMs; advanced ATM switching; high-speed dynamic reference circuit; level margin; noise margin; single-ended ECL input interface circuit;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19981165
Filename
715264
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