Title :
A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed
Author :
Kim, Jin-Ki ; Sakui, Koji ; Lee, Sung-Soo ; Itoh, Yasuo ; Kwon, Suk-Chon ; Kana, Kazuhisa ; Lee, Ki-Jun ; Nakamura, Hiroshi ; Kim, Kang-Young ; Himeno, Toshihiko ; Kim, Jang-Rae ; Kanda, Kazushige ; Jung, Tae-Sung ; Oshima, Yoichi ; Suh, Kang-Deog ; Hashi
Author_Institution :
Memory Div., Samsung Electron. Co. Ltd., Kiheung, South Korea
fDate :
5/1/1997 12:00:00 AM
Abstract :
Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm2 and an effective cell size of 1.1 μm2
Keywords :
CMOS memory circuits; EPROM; cellular arrays; decoding; memory architecture; 0.4 micron; 2 mus; 40 MB/s; 64 Mbit; NAND flash memory; array architecture; effective cell size; effective program speed; full-chip burst read capability; incremental step pulse programming scheme; mass storage flash memories; page sensing time; precharged capacitive decoupling sensing scheme; random access time; read throughput; single-metal CMOS process; staggered row decoder scheme; CMOS process; Costs; Decoding; Delay; Digital cameras; Flash memory; Laboratories; Motion pictures; Solid state circuits; Throughput;
Journal_Title :
Solid-State Circuits, IEEE Journal of
