A programmable focal-plane MIMD image processor chip

Author

Etienne-Cummings, Ralph ; Kalayjian, Zaven Kevork ; Cai, Donghui

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

Volume

36

Issue

1

fYear

2001

fDate

1/1/2001 12:00:00 AM

Firstpage

64

Lastpage

73

Abstract

An 80×78 pixels vision chip for focal-plane image processing is presented. The chip employs a Multiple-Instruction-Multiple-Data (MIMD) architecture to provide five spatially processed images in parallel. The size, configuration, and coefficients of the spatial kernels are programmable. The chip´s architecture allows the photoreceptor cells to be small and parked densely by performing all computations on the read-out, away from the array. The processing core uses digitally programmed current-mode analog computation. Operating at 9.6 K frames/s in 800-lux ambient light, the chip consumes 4 mW from a 2.5-V power supply. Performing 11×11 spatial convolutions, an equivalent computation (5.5 bit scale-accumulate) rate of 12.4 GOPS/mW is achieved using 22 mm² in a 1.2-μm CMOS process. The application of the chip to line-segment orientation detection is also presented

Keywords

CMOS integrated circuits; computer vision; convolution; edge detection; focal planes; parallel processing; programmable circuits; 1.2 micron; 2.5 V; 4 mW; 6240 pixel; 78 pixel; 80 pixel; CMOS process; digitally programmed current-mode analog computation; focal-plane MIMD image processor; line-segment orientation detection; photoreceptor cells; processing core; spatial convolutions; spatially processed images; vision chip; Analog computers; Biology computing; Cellular neural networks; Circuits; Computer architecture; High-resolution imaging; Image processing; Kernel; Pixel; Read-write memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.896230

Filename

896230