Title :
An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique
Author :
Liu, Ming-Huang ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
1/1/2001 12:00:00 AM
Abstract :
An 8-bit 10-MS/s folding and interpolating analog-to-digital converter (ADC) using the continuous-time auto-zero technique is presented. Compared with the conventional architecture, it can improve the nonlinear errors and enhance the signal-to-noise-and-distortion ratio (SNDR). Both architectures have been fabricated on the same die of a 0.35-μm DPDM CMOS process and measured under the same conditions with a 2.7-V supply voltage and 10-MHz sampling rate. The continuous-time auto-zero architecture shows an ENOB of 7.7 bits while the conventional one shows 5.8 bits
Keywords :
CMOS integrated circuits; analogue-digital conversion; 0.35 micron; 10 MHz; 2.7 V; 8 bit; DPDM CMOS process; ENOB; circuit architecture; continuous-time auto-zero technique; folding and interpolating analog-to-digital converter; nonlinear error; signal-to-noise-and-distortion ratio; CMOS technology; Capacitance; Circuits; Communication systems; Distributed amplifiers; Drives; Hard disks; Helium; Signal generators; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
