A 700-Mb/s/pin CMOS signaling interface using current integrating receivers

Author

Sidiropoulos, Stefanos ; Horowitz, Mark

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

32

Issue

5

fYear

1997

fDate

5/1/1997 12:00:00 AM

Firstpage

681

Lastpage

690

Abstract

A high speed CMOS signaling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes I-V push-pull drivers, a delay line phase-locked loop (PLL), and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception, a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8 μm CMOS technology achieve transfer rates of 740 Mb/s/pin operating from a 3.3 V supply with a bit error rate of less than 10^-14

Keywords

CMOS integrated circuits; data communication; digital communication; driver circuits; integrating circuits; mixed analogue-digital integrated circuits; multiprocessor interconnection networks; phase locked loops; receivers; signal sampling; timing circuits; 0.8 micron; 1 V; 3.3 V; 700 to 740 Mbit/s; BER; CMOS signaling interface; I-V push-pull drivers; bit error rate; current integrating receivers; current-integrating input pin sampler; data sampling; delay line PLL; high speed interface; multiprocessor interconnection networks; noise immunity; phase-locked loop; Bandwidth; CMOS technology; Clocks; Delay lines; Integrated circuit interconnections; Integrated circuit technology; Phase locked loops; Sampling methods; Semiconductor device noise; Transmitters;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.568834

Filename

568834