DocumentCode :
1427868
Title :
Technique for lower power dissipation in D-latch
Author :
Ong, Geok Ling ; Liu, Po-ching
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
Volume :
34
Issue :
18
fYear :
1998
fDate :
9/3/1998 12:00:00 AM
Firstpage :
1733
Lastpage :
1735
Abstract :
A special waveform to replace the power supply of a modified D-latch is presented. The power supply only exists when it is needed. Hence, the amount of switching at certain nodes is reduced. Furthermore, the voltage ramp in the power supply waveform enables energy recovery. HSPICE simulations show that the power consumption has been reduced by between 11.4 and 64.2%
Keywords :
flip-flops; logic design; D-latch; HSPICE simulations; energy recovery; power consumption; power dissipation reduction; power supply waveform; switching reduction; voltage ramp;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19981207
Filename :
715353
Link To Document :
بازگشت