Title :
Gate tolerances in sequential circuits
Author :
Duncan, F.G. ; Zissos, D.
Author_Institution :
University of Calgary, Department of Mathematics, Statistics & Computing Science, Calgary, Canada
fDate :
2/1/1971 12:00:00 AM
Abstract :
Maximum gate tolerances in sequential circuits are shown to be a direct function of the delays associated with the primary and secondary signals in critical races. Steps for allowing a gate-speed tolerance of up to ±33¿% to be accommodated in minimal designs are introduced.
Keywords :
hazards and race conditions; sequential circuits; circuit misoperation; critical races; gate tolerance calculation; hazard and race conditions; sequential circuits;
Journal_Title :
Electrical Engineers, Proceedings of the Institution of
DOI :
10.1049/piee.1971.0056
