Title :
A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application
Author :
Lee, Seog-Jun ; Kim, Beomsup ; Lee, Kwyro
Author_Institution :
Design Lab., Hyundai Electron. Ind. Co. Ltd., Kyungki, South Korea
fDate :
5/1/1997 12:00:00 AM
Abstract :
This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-μm CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of ±25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm2, the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter
Keywords :
CMOS integrated circuits; UHF integrated circuits; frequency synthesizers; integrated circuit noise; land mobile radio; mixed analogue-digital integrated circuits; phase locked loops; voltage-controlled oscillators; 0.8 micron; 125 mW; 5 V; 700 MHz to 1 GHz; CMOS technology; VCO; differential schemes; fully monolithic PLL frequency synthesizer; low-noise UHF frequency synthesizer; mobile communication application; static logic; tuning range; voltage controlled oscillator; CMOS logic circuits; CMOS technology; Circuit optimization; Frequency synthesizers; Integrated circuit technology; Logic circuits; Logic design; Phase locked loops; Tuning; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
