• DocumentCode
    1429831
  • Title

    From Layout Directly to Simulation: A First-Principle-Guided Circuit Simulator of Linear Complexity and Its Efficient Parallelization

  • Author

    He, Qing ; Chen, Duo ; Jiao, Dan

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • Volume
    2
  • Issue
    4
  • fYear
    2012
  • fDate
    4/1/2012 12:00:00 AM
  • Firstpage
    687
  • Lastpage
    699
  • Abstract
    In this paper, guided by electromagnetics-based first principles, the authors develop a transient simulator that allows for the simulation of an integrated circuit including both nonlinear devices and the layout of the linear network in linear complexity. The proposed circuit simulator rigorously captures the coupling between nonlinear circuits and the linear network. In addition, it bypasses the step of circuit extraction, producing a resistor-inductor-capacitor representation of the linear network without any numerical computation. Moreover, it permits an almost embarrassingly parallel implementation on a many-core computing platform, and hence enabling linear speedup. Application to die-package co-simulation as well as very large-scale on-chip circuits involving over complementary metal-oxide semiconductor transistors and interconnects having hundreds of millions of unknowns has demonstrated the superior performance of the proposed first-principle-guided circuit simulator.
  • Keywords
    CMOS integrated circuits; circuit simulation; linear network synthesis; complementary metal-oxide semiconductor transistors; die-package cosimulation; electromagnetics-based first principles; first-principle-guided circuit simulator; integrated circuit; linear complexity; linear network; nonlinear devices; resistor-inductor-capacitor representation; transient simulator; Equations; Integrated circuit modeling; Layout; Mathematical model; Nonlinear circuits; Vectors; Circuit simulation; electromagnetic simulation; linear complexity; linear speedup; multi-core; nonlinear circuits; parallel computing; time-domain finite-element method;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging and Manufacturing Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    2156-3950
  • Type

    jour

  • DOI
    10.1109/TCPMT.2011.2179547
  • Filename
    6138296