Linearity improvement of open-loop NMOS source-follower sample and hold circuits

Author

Shirazi, A.N. ; Mirhaj, S.A. ; Ashtiani, S.J. ; Shoaei, Omid

Author_Institution

Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran

Volume

5

Issue

1

fYear

2011

fDate

1/1/2011 12:00:00 AM

Firstpage

1

Lastpage

7

Abstract

A new open-loop sample and hold (S/H) circuit is proposed for high-speed sampled data applications. The open-loop S/H circuit uses the source-follower configuration, for its high speed, low power consumption, small area and low circuit complexity. In order to achieve high linearity, a body effect cancellation technique is proposed which is based on proper modulation of the bias current of the source-follower transistor. Simulated by HSPICE with a standard BSIM3v3 0.18 μm CMOS technology, the pseudo-differential open-loop S/H achieves over 76 dB spurious free dynamic range (SFDR) for a 1.6 V_ppd output at 200 MHz sampling frequency. The S/H dissipates 12.5 mW power from a 1.8 V supply.

Keywords

CMOS analogue integrated circuits; MOSFET; circuit complexity; sample and hold circuits; BSIM3v3 CMOS technology; HSPICE; body effect cancellation technique; frequency 200 MHz; high speed low power consumption; low circuit complexity; open-loop NMOS source-follower sample and hold circuits; power 12.5 mW; pseudo-differential open-loop S/H circuit; size 0.18 mum; source-follower transistor; spurious free dynamic range; voltage 1.6 V; voltage 1.8 V;

fLanguage

English

Journal_Title

Circuits, Devices & Systems, IET

Publisher

iet

ISSN

1751-858X

Type

jour

DOI

10.1049/iet-cds.2009.0312

Filename

5692790