Title :
Advanced Method for Defect Characterization Using Fail Bit Analysis and Critical Area Simulation
Author :
Matsumoto, C. ; Hamamura, Y. ; Chida, T. ; Tsunoda, Y. ; Go, N. ; Uozaki, H. ; Miyazaki, I. ; Kamohara, S. ; Kaneko, Y. ; Kanamitsu, K.
Author_Institution :
Production Eng. Res. Lab., Hitachi, Ltd., Yokohama, Japan
fDate :
5/1/2011 12:00:00 AM
Abstract :
We propose an advanced approach to accurately estimate wafer-wafer variation of random defect density in each process layer (D0l) using fail bit analysis and critical area simulation. The proposed method formulates D0l estimation using a linear programming model with constraint set of D0l is positive. The D0l estimation results are consistent with the test vehicles. We also illustrate some effective application results for yield improvement activities in the semiconductor manufacturing line.
Keywords :
failure analysis; linear programming; semiconductor device reliability; semiconductor device testing; semiconductor industry; critical area simulation; defect characterization; fail bit analysis; linear programming model; semiconductor manufacturing line; test vehicles; wafer-wafer variation estimation; Accuracy; Estimation; Integrated circuit modeling; Layout; Manufacturing; Semiconductor device modeling; Systematics; Critical area analysis; fail bit map; integrated circuit layout; random defects;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
DOI :
10.1109/TSM.2011.2106168
