Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories

Author

Kawahara, Takayuki ; Kobayashi, Takashi ; Jyouno, Yusuke ; Saeki, Syun-ichi ; Miyamoto, Naoki ; Adachi, Tetsuo ; Kato, Masstaka ; Sato, Akihilko ; Yugami, Jiro ; Kume, Hitoshi ; Kimura, Katsutaka

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

31

Issue

11

fYear

1996

fDate

11/1/1996 12:00:00 AM

Firstpage

1590

Lastpage

1600

Abstract

This paper proposes circuit technologies adaptable to the potential scalability of flash memory cells and an accurate internal voltage generator for use under low voltage operation. A circuit with a relaxed layout pitch, bit-line clamped sensing multiplex, and intermittent burst data transfer (four phases with 500 ns/20 ns) is proposed for a three times feature-size pitch. A 5-μA low-power dynamic band-gap generator with voltage boosted by using triple-well bipolar transistors and voltage-doubler charge pumping, for accurate generation of 10 to 20 V, are also proposed for use at V_vv of under 2.5 V. To demonstrate the circuit feasibility, a 105.9-mm² 128-Mb experimental chip was fabricated using 0.25-μm technology

Keywords

EPROM; integrated memory circuits; multiplexing; signal generators; 0.25 micron; 10 to 20 V; 128 Mbit; 2.5 V; bit-line clamped sensing multiplex; circuit scalability; flash memory; high voltage generator; intermittent burst data transfer; low voltage operation; low-power dynamic band-gap generator; relaxed layout pitch; triple-well bipolar transistor; voltage-doubler charge pumping; Associate members; Bipolar transistors; Cellular phones; Charge pumps; Circuits; Dynamic voltage scaling; Flash memory; Flash memory cells; Low voltage; Paper technology; Photonic band gap; Power supplies; Scalability; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1996.542303

Filename

542303