A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM

Author

Toyoshima, Hisashi ; Kuhara, Shigeru ; Takeda, Koichi ; Nakamura, Kazuyuki ; Okamura, Hitoshi ; Takada, Masahide ; Suzuki, Hisamitsu ; Yoshida, Hiroshi ; Yamazaki, Tohru

Author_Institution

Microelectron. Res. Labs., NEC Corp., Sagamihara, Japan

Volume

31

Issue

11

fYear

1996

fDate

11/1/1996 12:00:00 AM

Firstpage

1610

Lastpage

1617

Abstract

A 0.3-μm 4-Mb BiCMOS SRAM with a 6-ns access time at a minimum supply voltage of 1.5 V has been developed. Circuit technologies contributing to the low-voltage, high-speed operations include: (1) boost-BiNMOS gates for address decoding circuits; (2) an optimized word-boost technique for a highly-resistive-load memory cell; (3) a stepped-down CML cascoded bipolar sense amplifier; (4) optimum boost-voltage detection circuits with dummies for boost-voltage generators

Keywords

BiCMOS memory circuits; SRAM chips; 0.3 micron; 1.5 V; 4 Mbit; 6 ns; BiCMOS SRAM; LV static RAM; address decoding circuits; boost-BiNMOS gates; boost-voltage generators; high-speed operation; highly-resistive-load memory cell; low-voltage operation; optimized word-boost technique; optimum boost-voltage detection circuits; stepped-down CML cascoded bipolar sense amplifier; Associate members; BiCMOS integrated circuits; Capacitance; DC generators; Decoding; Delay effects; Inverters; Laboratories; Leakage current; MOSFET circuits; National electric code; Operational amplifiers; Random access memory; Ultra large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1996.542305

Filename

542305