• DocumentCode
    1430514
  • Title

    A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

  • Author

    Sakashita, Narumi ; Nitta, Yasuhiko ; Shimomura, Ken´ichi ; Okuda, Fumigiro ; Shimano, Hiroki ; Yamakawa, Satoshi ; Tsukude, Masaki ; Arimoto, Kazutami ; Baba, Shinji ; Komori, Shinji ; Kyuma, Kazuo ; Yasuoka, Akihiko ; Abe, Haruhiko

  • Author_Institution
    Adv. Technol. R & D Center, Mitsubishi Electr. Corp., Itami, Japan
  • Volume
    31
  • Issue
    11
  • fYear
    1996
  • fDate
    11/1/1996 12:00:00 AM
  • Firstpage
    1645
  • Lastpage
    1655
  • Abstract
    This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 μm2 cell and 581.8 mm2 small die area are achieved using 0.15-μm CMOS technology. The ×61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described
  • Keywords
    CMOS memory circuits; DRAM chips; built-in self test; memory architecture; 0.15 micron; 1 Gbit; 1.6 GB/s; 200 MHz; BGA type chip-scale-package; CMOS technology; DRAM array; built-in self-test circuit; data transfer rate; distributed bank architecture; hierarchical square-shaped memory block; high-speed operation; memory capacity; synchronous DRAM; three-dimensional graphics frame memory; time sharing; Automatic testing; Built-in self-test; CMOS technology; Chip scale packaging; Circuit testing; Clocks; Costs; Graphics; Layout; Pins; Random access memory; SDRAM; Time sharing computer systems; Wiring;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1996.542309
  • Filename
    542309