Title :
200-MHz superscalar RISC microprocessor
Author :
Vasseghi, Nader ; Yeager, Kenneth ; Sarto, Egino ; Seddighnezhad, M.
Author_Institution :
Silicon Graphics Comput. Syst., Mountain View, CA, USA
fDate :
11/1/1996 12:00:00 AM
Abstract :
Design and implementation details of the MIPS R10000, 200-MHz, 64-b superscalar dynamic issue RISC microprocessor is presented. It fetches and decodes four instructions per cycle and dynamically issues them to five fully pipelined, low latency execution units, Its hierarchical nonblocking memory system helps hide memory latency with two levels of set-associative, write-back caches. The processor has over 6.8 M transistors and is built in 3.3-V, 0.30 μm, four-layer metal CMOS technology with under 30 W of power consumption. The processor delivers peak performance of Spec95int of 9 and Spec95fp of 19 operating at 200 MHz. Clock and power distribution as well as circuit design techniques of several blocks are addressed
Keywords :
CMOS digital integrated circuits; microprocessor chips; pipeline processing; reduced instruction set computing; timing; 0.3 micron; 200 MHz; 3.3 V; 30 W; 64 bit; MIPS R10000; circuit design techniques; clock distribution; dynamic issue; four-layer metal CMOS technology; hierarchical nonblocking memory system; pipelined low latency execution units; power distribution; set-associative write-back caches; superscalar RISC microprocessor; CMOS process; CMOS technology; Circuit synthesis; Clocks; Decoding; Delay; Energy consumption; Microprocessors; Power distribution; Reduced instruction set computing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1996.542312
