Design of ATM AAL1 SAR for circuit emulation

Author

Lee, Yih-Chang ; Kao, Tain-Lieng ; Wu, Kou-Tan

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ., Taiwan

Volume

46

Issue

9

fYear

1998

fDate

9/1/1998 12:00:00 AM

Firstpage

1117

Lastpage

1121

Abstract

The asynchronous transfer mode (ATM) adaptation layer type 1 (AAL1) segmentation and reassembly (SAR) are designed and implemented by the field programmable gate array (FPGA). The SAR header is generated and processed in the FPGA and the SAR payload is stored in an external first-in-first-out (FIFO) device. A method to recover the source clock, called synchronous residual time stamp (SRTS), is implemented. The designed AAL1 SAR FPGA is properly tested in a prototype circuit board

Keywords

asynchronous transfer mode; field programmable gate arrays; integrated circuit design; printed circuit layout; synchronisation; transport protocols; ATM AAL1 SAR; FIFO device; SAR header; adaptation layer type 1; asynchronous transfer mode; circuit emulation; design; external first-in-first-out device; field programmable gate array; prototype circuit board; segmentation and reassembly; source clock; synchronous residual time stamp; Asynchronous transfer mode; Circuit testing; Clocks; Emulation; Field programmable gate arrays; Frequency; Jitter; Printed circuits; Protocols; Prototypes;

fLanguage

English

Journal_Title

Communications, IEEE Transactions on

Publisher

ieee

ISSN

0090-6778

Type

jour

DOI

10.1109/26.718553

Filename

718553