Architecture of 23GOPS video signal processor with programmable systolic array

Author

Miyake, Jiro ; Urano, Miki ; Inoue, Genichiro ; Yano, Junichi ; Tsubata, Shintaro ; Nishiyama, Tamotsu ; Yamaguchi, Seiji

Author_Institution

Semicond. Dev. Div., Matsushita Elect. Ind. Co. Ltd., Kyoto, Japan

Volume

45

Issue

9

fYear

1998

fDate

9/1/1998 12:00:00 AM

Firstpage

1272

Lastpage

1278

Abstract

This paper describes an architecture of 23GOPS real-time video signal processor. In order to achieve high computational power and high data bandwidth for real-time video signal processing, we adopt a unique architecture based on a programmable systolic array with 90 video processing elements (VPEs). The VPE array realizes high processing ability and high flexibility by a simple structure of the VPE and a time-division multiple-operation scheme. It allows the processor to be applied to various real-time video signal processing like HD-TV (MUSE) decoding. The processor, called the digital filtering array, has been fabricated in 0.35-μm CMOS three-metal-layer technology and achieves 23GOPS at 129.6 MHz operating frequency. Four million transistors are integrated in 13.61 mm×13.07 mm die size

Keywords

CMOS digital integrated circuits; digital signal processing chips; systolic arrays; video signal processing; 0.35 micron; 129.6 MHz; CMOS three-metal-layer technology; HDTV MUSE decoding; VPE array; computational power; data bandwidth; digital filtering array; parallel architecture; programmable systolic array; real-time video signal processor; time-division multiple-operation; Bandwidth; CMOS process; CMOS technology; Computer architecture; Decoding; Digital filters; Filtering; Signal processing; Systolic arrays; Video signal processing;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.718595

Filename

718595