A simulator core for charge-pump PLLs

Three techniques are introduced to enhance the simulation speed of communication systems including a charge-pump phase-locked loop. First, a technique using exact explicit solutions of differential equations is extended to nonuniformly sampled circuits. This allows arbitrarily large time and voltage steps in an event-driven simulator without introducing numerical errors. Then, event prediction using mathematical limits enables large time steps and unlimited accuracy. Finally, an interpolator is combined with delay-partitioning to reduce the required oversampling rate. High accuracy is demonstrated with as low as four events per cycle of the system clock and an oversampling ratio of 3