DocumentCode :
1431670
Title :
Performance of multistage bus networks for a distributed shared memory multiprocessor
Author :
Bhuyan, Laxmi N. ; Iyer, Ravi R. ; Askar, Tahsin ; Nanda, Ashwini K. ; Kumar, Mohan
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Volume :
8
Issue :
1
fYear :
1997
fDate :
1/1/1997 12:00:00 AM
Firstpage :
82
Lastpage :
95
Abstract :
A multistage bus network (MEN) is proposed to overcome some of the shortcomings of the conventional multistage interconnection networks (MINs), single bus, and hierarchical bus interconnection networks. The MBN consists of multiple stages of buses connected in a manner similar to the MINs and has the same bandwidth at each stage. A switch in an MBN is similar to that in a MIN switch except that there is a single bus connection instead of a crossbar. MBNs support bidirectional routing and there exists a number of paths between any source and destination pair. The authors develop self routing techniques for the various paths, present an algorithm to route a request along the path with minimum distance, and analyze the probabilities of a packet taking different routes. Further, they derive a performance analysis of a synchronous packet-switched MBN in a distributed shared memory environment and compare the results with those of an equivalent bidirectional MIN (BMIN). Finally, they present the execution time of various applications on the MBN and the BMIN through an execution-driven simulation. They show that the MBN provides similar performance to a BMIN while offering simplicity in hardware and more fault-tolerance than a conventional MIN
Keywords :
distributed memory systems; fault tolerant computing; multistage interconnection networks; network routing; packet switching; performance evaluation; shared memory systems; system buses; virtual machines; algorithm; bandwidth; bidirectional routing; distributed shared memory multiprocessor; execution time; execution-driven simulation; fault tolerance; hardware; multistage bus network performance; packet routing; performance analysis; request routing; self routing techniques; single bus connection; switch; synchronous packet-switched multistage bus network; Algorithm design and analysis; Bandwidth; Computational modeling; Computer Society; Hardware; Multiprocessor interconnection networks; Performance analysis; Routing; Switches; Telecommunication traffic;
fLanguage :
English
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9219
Type :
jour
DOI :
10.1109/71.569657
Filename :
569657
Link To Document :
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