A robust to PVT variations low-voltage low-power current mirror

In this paper the design of a very low-voltage current mirror with an enhanced output resistance is presented. The mirror is designed using transistors in weak-inversion region, which allows operating with reduced supply voltage. With the use of multiple feedback loops, parameters such as minimum output voltage and output resistance are kept constant with respect to supply voltage, temperature and fabrication process variations (PVT variations). The mirror is biased at 0.5 V and is designed in a standard 0.18 μm technology. As a result, the circuit needs only 60 mV and 80 mV to saturate for NMOS and PMOS implementations respectively, with a maximum variation of 10 mV for all process corners and temperatures between -40 °C and 120 °C, and supply voltages between 0.45 V and 0.55 V. Finally, the mirror was used in a one-stage fully-differential OTA, for which a gain of 75 dB was achieved.