DocumentCode :
1432093
Title :
Hierarchical pipelining and folding of QRD-RLS adaptive filters and its application to digital beamforming
Author :
Gao, Lijun ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Volume :
47
Issue :
12
fYear :
2000
fDate :
12/1/2000 12:00:00 AM
Firstpage :
1503
Lastpage :
1519
Abstract :
This paper presents a novel hierarchical approach for pipelining and folding the large CORDIC-based systolic array of a QR decomposition-based recursive least square algorithm (QRD-RLS) adaptive filter to a small fixed size array. With the annihilation-reordering look-ahead transformation, the iteration bound of a QRD-RLS adaptive filter can be reduced linearly with respect to the look-ahead factor. This paper presents, for the first time, how to pipeline and fold such a look-ahead transformed QRD-RLS adaptive filter. Unlike the previously published algorithms, this approach has low complexity and can result in a physical array of any size. In addition, a mathematical model for evaluating these transformations is developed. Using this model, it is shown how a combination of look-ahead, pipelining, and folding transformations can lead to a large increase in throughput and large reduction in area or power consumption. Therefore, the proposed approach is of great significance for application-specific IC chip design, high-level hardware synthesis, and special-purpose processor design. The optimally designed QRD-RLS adaptive filters can be used for adaptive digital beamforming applications, which play an important role in radar, sonar, and mobile/wireless communication systems
Keywords :
VLSI; adaptive filters; application specific integrated circuits; array signal processing; high level synthesis; least squares approximations; pipeline processing; recursive estimation; systolic arrays; ORDIC-based systolic array; QR decomposition-based recursive least square algorithm; QRD-RLS adaptive filters; annihilation-reordering look-ahead transformation; application-specific IC chip design; digital beamforming; fixed size array; folding transformations; hierarchical pipelining; high-level hardware synthesis; look-ahead factor; mathematical model; special-purpose processor design; throughput; Adaptive arrays; Adaptive filters; Application specific integrated circuits; Energy consumption; Integrated circuit synthesis; Least squares methods; Mathematical model; Pipeline processing; Systolic arrays; Throughput;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7130
Type :
jour
DOI :
10.1109/82.899644
Filename :
899644
Link To Document :
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