• DocumentCode
    1432099
  • Title

    An efficient architecture for multi-dimensional convolution

  • Author

    Elnaggar, A. ; Aboelaze, M.

  • Author_Institution
    Dept. of Electr. Eng., Sultan Qaboos Univ., Muscat, Oman
  • Volume
    47
  • Issue
    12
  • fYear
    2000
  • fDate
    12/1/2000 12:00:00 AM
  • Firstpage
    1520
  • Lastpage
    1523
  • Abstract
    This paper presents modified parallel architectures for multidimensional (m-d) convolution. We show that for two-dimensional (2-d) convolutions, with careful design, the number of lower-order 2-d convolutions can be reduced from nine to six with a computation saving of 33%. However, the original speed of the computations is not affected. The proposed partitioning strategy results in a core of data-independent convolution computations, and can be generalized to the m-d convolution. The resulting very large scale integration networks have very simple modular structure, highly regular topology, and use simple arithmetic devices
  • Keywords
    VLSI; convolution; digital arithmetic; logic partitioning; multidimensional signal processing; parallel architectures; arithmetic devices; computation saving; data-independent convolution computations; lower-order 2-d convolutions; modified parallel architectures; modular structure; multi-dimensional convolution; partitioning strategy; regular topology; very large scale integration network; Arithmetic; Computer architecture; Convolution; Matrix decomposition; Multidimensional systems; Network topology; Parallel architectures; Tensile stress; Two dimensional displays; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.899645
  • Filename
    899645